Samsung debuts next-gen memory chips for AI systems 

Samsung Electronics has unveiled mock-ups of two new memory chip designs, zHBM and zNAND-O, along with an ultrahigh-capacity NAND flash chip, as it lays out a technology road map aimed at meeting surging memory demand from artificial intelligence systems.

The chips were shown for the first time at Future of Memory and Storage 2026, an industry conference that runs until Thursday in Santa Clara, California.

High bandwidth memory (HBM) is built by stacking multiple layers of dynamic random-access memory (DRAM) chips and connecting them with thousands of tiny vertical wires, allowing data to move between layers far faster than in conventional memory. This speed has made HBM the memory of choice for AI accelerators. 

Samsung's zHBM design pushes that concept further. Where HBM chips currently sit beside an AI accelerator on the same package, zHBM stacks memory directly on top of the accelerator, shortening the distance data has to travel. Samsung said the design allows systems to run up to eight times faster than those using HBM5, while improving power efficiency by up to three times and reducing thermal resistance by more than half. The zHBM can also be customized, letting chipmakers add specialized circuitry to expand storage capacity or boost performance for individual customers.

Samsung also introduced zNAND-O, a next-generation version of NAND flash memory used for long-term data storage. Unlike zHBM, which is built for AI accelerators, zNAND-O is designed for on-device AI — artificial intelligence tasks processed locally on a device rather than in a remote data center. The chip combines conventional NAND's layered structure with a bonding technique that packages four or eight semiconductor chips together, boosting storage density while reducing physical size.

Separately, Samsung unveiled the V10 BV-NAND, its 10th-generation V-NAND flash chip and the first in the industry to stack over 400 layers. The company achieved the height using wafer bonding, a technique that fuses separately manufactured silicon wafers together vertically rather than building all layers on a single wafer. Samsung said the approach increases storage density by about 58 percent compared with its previous generation chip, the V9, while also improving read and write speeds.

Beyond the new chips, Samsung showcased HBM4E, a mock-up of HBM5 with a new cooling technology called the heat path block, and LPDDR5X-PIM, a memory chip the company says is the first in the industry to perform calculations inside the memory itself rather than shuttling data to a separate processor.

Samsung became the first chipmaker to begin mass shipments of HBM4 in February and supplied HBM4E samples to customers in May. The company holds the largest DRAM market share, at 39 percent, according to data for the second quarter of 2026 from market tracker Counterpoint Research, followed by SK hynix at 26 percent, Micron at 25 percent and CXMT at 7 percent.

BY LEE JAE-LIM [lee.jaelim@joongang.co.kr]